Meta has disclosed architectural roadmaps and rollout targets for four successive generations of its proprietary Meta Training and Inference Accelerator: MTIA 300, MTIA 400, MTIA 450, and MTIA 500. Built in partnership with Broadcom, the roadmap expands Meta’s custom silicon effort beyond earlier ranking and recommendation inference into recommendation training and specialized generative AI workloads. Across the full four-chip progression, Meta reports an aggregate 4.5-fold increase in high-bandwidth memory (HBM) bandwidth and a 25-fold expansion in compute FLOPS from MTIA 300's MX8 to MTIA 500's MX4.

Staged Deployments and Workload Shifts

In its March announcement, Meta mapped each generation to specific workloads and rollout phases:

  • `MTIA 300`: Designed for ranking and recommendation (R&R) training; currently operating in live production. Built with one compute chiplet, two network chiplets, and dedicated message engines.
  • `MTIA 400`: Adds support for general generative AI alongside R&R workloads, using two compute chiplets in a 72-accelerator scale-up rack domain. Meta stated it has completed lab testing and is preparing for data center deployment.
  • `MTIA 450`: Focuses specifically on generative AI inference; scheduled for mass deployment in early 2027.
  • `MTIA 500`: Further optimizes generative AI inference with a 2x2 grid of smaller compute chiplets, an SoC chiplet, and two network chiplets; scheduled for mass deployment in 2027.

Memory Bandwidth and Low-Precision Formats

Meta tailored the later chips to alleviate generative inference decode and mixture-of-experts (MoE) compute bottlenecks. According to Meta, HBM bandwidth doubles from MTIA 400 to MTIA 450, and increases another 50% in MTIA 500, which also adds up to 80% higher HBM capacity.

On the compute side, Meta pairs higher memory throughput with reduced precision. MTIA 400 supports enhanced MX8 and MX4 data types and claims a 400% FP8 FLOPS increase over MTIA 300. For MTIA 450, Meta reported a 75% increase in MX4 FLOPS over MTIA 400, delivering six times the MX4 FLOPS of FP16/BF16, along with mixed low-precision execution designed to avoid runtime software format conversion. MTIA 500 claims a further 43% gain in MX4 FLOPS over MTIA 450.

Shared Rack Infrastructure and Software Integration

To support a targeted six-month release cadence, Meta designed MTIA 400, MTIA 450, and MTIA 500 to drop into identical chassis, rack, and network infrastructure. The 72-device rack-scale systems support facility liquid cooling as well as air-assisted liquid cooling (AALC) for deployment into legacy data centers.

The chips run on a PyTorch-native software stack using Torch FX, torch.compile, and Triton backends, with collective operations coordinated through Meta’s Hoot Collective Communications Library (HCCL). Meta also developed custom vLLM plugins for FlashAttention and fused LayerNorm kernels to support prefill-decode disaggregation and continuous batching on internal clusters.