Micron announced at GTC 2026 that it began volume shipments of its 36GB 12-high (12H) HBM4 memory in the first quarter of calendar year 2026. Designed for Nvidia Vera Rubin systems, the memory targets the throughput bottlenecks that constrain accelerator execution during large-scale AI training and inference workloads.

Memory Bandwidth Claims and Packaging Milestones

Accelerator throughput depends directly on memory bandwidth to keep compute units fed with model weights and activations. Micron claims its HBM4 stacks achieve pin speeds exceeding 11 Gbps, providing more than 2.8 TB/s of bandwidth per cube. Micron reports a 2.3-fold bandwidth increase over 36GB 12H HBM3E. Its pin-speed claim draws on internal testing and customer test vehicles; the reported power-efficiency gain of more than 20% comes from an internal power calculator under specified workload conditions.

Beyond its 12-high volume modules, Micron has also started shipping customer samples of a 48GB 16-high (16H) HBM4 cube. The 16-die stack yields a 33% increase in capacity per HBM placement compared to the 36GB 12H offering, though the company identifies this higher-density part as currently sampling rather than in volume production.

System Memory and PCIe Gen6 Companion Tiers

Alongside on-package HBM4, Micron reported high-volume production for two companion products serving separate system-level memory and storage tiers across rack architectures:

  • Host system memory: Micron is mass-producing a 192GB SOCAMM2 module designed for Nvidia Vera Rubin NVL72 rack systems and standalone Nvidia Vera CPU platforms. Micron states the format supports up to 2TB of memory and 1.2 TB/s of bandwidth per CPU socket, forming part of a broader SOCAMM2 portfolio spanning 48GB to 256GB capacities.
  • Storage and ingest: Micron placed its 9650 PCIe Gen6 data center SSD into high-volume production. Optimized for liquid-cooled deployments and agentic AI workloads on the Nvidia BlueField-4 STX reference architecture, Micron rates the drive at up to 28 GB/s in sequential read throughput and 5.5 million random read IOPS. According to Micron, this doubles the read performance of Gen5 drives at twice the performance per watt.

These companion components handle platform-level duties distinct from HBM: SOCAMM2 provides dense host-level memory for CPU contexts, while Gen6 flash handles streaming ingestion into the computing cluster.